HBM Value Chain Pass-Through: Mapping Article 2 Onto Names

NVDA is the most direct bet — because the company burning the most HBM is NVDA itself. It isn't passively consuming HBM as a customer; it's the designer of this HBM-concentration arms race. In the new Vera Rubin servers, every GPU carries 12 HBM4 stacks; the 2027 Rubin Ultra pushes per-package HBM capacity to 1 TB. In other words, the more NVDA ships, the more HBM SK Hynix / Samsung / Micron get pulled into selling.

The pull is already showing up on the revenue line: FY26 Q1 data center revenue $81.6B / +85% YoY; Q2 NVDA itself guided $91B; of the $1T order book, $172.6B is already locked to convert in H1. Gross margin 75% — the compound output of vertical integration + CUDA software lock + NVLink network closure, with no visible ceiling near term.

If you believe Article 2's “HBM TAM expands” conclusion holds at the industry level, you don't need to guess which HBM vendor gets the biggest slice — betting on NVDA is betting on all three HBM vendors at once, because NVDA is the force dragging them to burn.

(a) CoWoS-L 4x reticle yield pressure — TSMC pushing CoWoS to 130-150K wpm by end-2026 is unprecedented complexity (Article 2 errata flagged this); (b) whether CUDA's moat erodes under Kimi Linear and similar alternative architectures — Article 2 Ch 3 judges no material impact through 2026-2027.

Vera Rubin actual first-ship timing (currently H2 2026 guide); CoWoS-L yield; HBM concentration ramp on NVL72 / NVL144 / NVL576.

AMD is the second player you can bet on directly for HBM volume, but the bet logic differs from NVDA — not “AMD beats NVDA” but “AMD is a credible second-source that gets a structural share alongside NVDA.” That's already cashing out in the 12 GW of total deals: OpenAI 6 GW + Meta 6 GW, with first ship starting H2 2026. With hyperscalers actively asking for second-source this cycle, AMD doesn't have to out-engineer NVDA to win this slice.

The more interesting twist is per-chip HBM consumption. AMD MI455X carries 432 GB HBM4 per chip — higher than NVDA Rubin's 288 GB in the same generation, only beaten by next year's Rubin Ultra 1 TB. In other words, selling one MI455X drives more HBM than selling one same-generation NVDA chip; AMD is, in this generation, the densest HBM per accelerator.

On the supply side, Samsung locked in primary HBM4 supplier status on MI455X via the AMD-Samsung MoU on 2026-03-18 — supply-chain confirmation for AMD, and precisely the Micron-individual “discount” data point Article 2 flagged. Lisa Su's positioning of MI450 as “inference-first” in May 2026 also takes half the pressure off “must beat NVDA's training stack” — 12 GW of volume, even inference-only, is a real structural bet.

One honest caveat: Theta's internal thesis downgraded AMD from bull to sell on 2026-05-11 at ~$465 (Q1 post-print +18.7% pre-market pop compressed risk-reward); current ~$495 already prices in most of the upside. So this is the “industry-level holds = AMD is a beneficiary” judgment, not the “buy AMD now” judgment — keep the two separate.

ROCm is still only 1/10 the size of CUDA by developer count; MI450 training-stack adoption at OpenAI / Meta won't be visible until Q4 2026. Theta internal thesis (2026-05-11) downgraded conviction from bull to sell around $465 — Q1 post-print +18.7% pre-market pop compressed risk-reward. This caveat needs to be on the record. Current ~$495 already prices in most of the upside.

Evidence of MI450 training-stack >25% adoption at OpenAI / Meta; Samsung MI455X HBM4 yield (Samsung 1c currently sub-60%, target 80% by H2 2026).

If you don't want to bet on a single accelerator, but instead on “the accelerator market fragmenting and every hyperscaler wanting its own ASIC,” AVGO is the player collecting the most design fees + royalties from that fragmentation.

Key insight: hyperscaler in-house chips (Google TPU, Meta MTIA, Microsoft Maia, AWS Trainium) don't cannibalize each other — Google won't switch to Trainium, Meta won't use Maia, each ramp is independent incremental demand. AVGO's grab isn't any one of them; it's the fact that “nearly every non-Maia hyperscaler ASIC includes AVGO's SerDes / NoC IP.” It is simultaneously inside 6+ hyperscaler ASIC programs — Google TPU (2031 long-term supply agreement), Meta MTIA (4-generation deal), OpenAI Titan (Mizuho estimate $150-200B), ByteDance, Fujitsu, Anthropic.

The revenue conversion shows the same pattern: FY26 Q2 AI semi guide $10.7B / +140% YoY, run-rate exiting the year at $42B+; Q4 FY25 backlog at $73B. That backlog curve is the most direct empirical validation of the “ASIC wave fan-out” thesis.

One-line takeaway of the two bets: NVDA earns from the GPU side; AVGO earns from “hyperscalers not wanting to use NVDA.” Both bet on the same HBM-expansion theme, but with mutually hedging risk profiles — which is why NVDA + AVGO is the classic two-name pair at the industry level.

(a) VMware renewal cliff (starting late 2026 / 2027, pricing +200-1,200% creating churn risk, though independent of AI semi revenue line); (b) NVDA Spectrum-X Photonics in 2H 2026 is an architectural challenge to AVGO CPO, but initially NVDA-only — no material impact before 2027.

OpenAI Titan ramp progress (revenue starts 2H 2026 — the key data point for AVGO's next step); detailed contract terms of the Google TPU 2031 long-term agreement.

MRVL is the #2 player in the ASIC wave — less diversified than AVGO, but with two distinct edges, both in places AVGO doesn't compete.

Edge #1: 800G optical DSPs. Marvell holds 70-80% global share in this market (the legacy of the 2021 Inphi acquisition), and is the first company to volume-ship 1.6T optical DSPs — all four flagship parts (Ara T / Ara X / Petra / Aquila M) on 3nm. AI data centers either use NVLink / UALink short-haul copper inside a rack, or optical interconnect for cross-rack long-haul — the latter basically can't bypass Marvell.

Edge #2: NVDA's $2B co-development agreement signed directly with MRVL on 2026-03-31, which flipped MRVL from “potential CPO substitute” to NVDA's own silicon photonics partner. Add Google's late-stage talks with MRVL in April 2026 about its own MPU + inference chip — that's MRVL's 4th hyperscaler customer locked in.

MRVL's real weakness has to be put on the table: the Trainium 3 socket has already gone to Alchip (after Trainium 2's RDL yield issues), and Alchip also won the Trainium 4 backend — meaning MRVL didn't lock in cross-generational continuity at AWS, and now has to backfill the lost share through Maia + Arke + Google MPU.

So the MRVL bet has a clear shape: more concentrated than AVGO, but each line is non-overlapping; lost AWS as a line, but NVDA silicon photonics + Google MPU are filling in. It's the “concentrated but clearly diversified-by-line” bet within the ASIC wave.

Trainium 3 socket already lost to Alchip (post Trainium 2 RDL issues), Alchip also won Trainium 4 backend — MRVL is not inter-generationally locked in at AWS. AWS still ~76% of data center revenue. ~$199 already reflects NVDA partnership + hyperscaler expansion — no margin of safety.

Revenue ramp on Maia 200 + Arke + Google MPU; speed of backfill from the Trainium loss.