Memory at the 2027 Crux: A Technical Reading of Micron's SCA Reframe

Why the bull and the bear are both right — and what has to resolve before either wins

Draft — Chapters 1 & 2 only.

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Chapter 1 — The Question

1.1 The price reaches the bull case before the bull case is built

On 2026-05-19, Melius Research raised its Micron Technology (MU) price target from $700 to $1,100 — a 57% lift in a single note. Citigroup raised its target from $425 to $840 the same day, nearly doubling. Bank of America was already at $950. HSBC analyst Ricky Seo wrote that the current memory upcycle is "running four to five years rather than the typical two to three." Melius's framing was higher still: "the AI memory cycle could continue through the end of the decade." By 2026-05-26, six sell-side desks — BofA, Citi, HSBC, CFRA, Mizuho, Melius — had converged on an $800-$1,100 target cluster.

These are not cyclical price targets. They are growth-stock price targets. The implicit re-rating is from mid-cycle EV/EBITDA, the regime that has governed memory valuations for two decades, to forward growth multiples, the regime that applies to NVIDIA, ASML, and TSMC. Within ten weeks the public discussion of Micron shifted from where is the cycle peak to is this even a cycle anymore.

1.2 What changed — a contract structure, named on the Q2 FY26 call

The proximate trigger is not the Samsung labor strike that bracketed the week the targets were raised; that catalyst has since resolved, with the Samsung union ratifying a tentative wage deal. The structural cause is a contract terminology that Sanjay Mehrotra introduced on Micron's 2026-03-18 Q2 FY26 earnings call: the Strategic Customer Agreement, or SCA. From Mehrotra's prepared remarks, verbatim:

"We are excited to have signed our first five-year SCA."

"LTAs have tended to be typically one-year agreements ... [an SCA] is a multiyear agreement with specific commitments over a multiyear time horizon for improved visibility and stability in our business model."

"These are meant to go across periods when the industry is very tight versus other parts of the industry environment ... they have robust provisions in them for us as well as for our customers."

The last sentence is load-bearing. Memory has been a cyclical industry because spot pricing collapses when supply normalizes — an extremely tight market becomes an oversupplied market within 12-18 months once new fabs come online, and the contract structure offers no insulation. If a five-year agreement with "robust provisions ... across periods when the industry is very tight versus other parts" is real and material, a meaningful share of Micron's HBM revenue is now contracted at terms that survive the downside of the next cycle. That is precisely the mechanism a cyclical-to-secular re-rating requires.

The phenomenon is not Micron-specific. The same week, SanDisk CEO David Goeckeler told Yahoo Finance that customers were "providing demand forecasts extending through 2028, prompting discussions about agreements lasting one to five years." Western Digital's CEO disclosed that HDD capacity was sold out for 2026 with some LTAs already extending into 2027 and 2028. Across DRAM, NAND, and HDD, the contract-tenor is extending in unison. This is industry structure, not corporate spin.

1.3 The thesis Theta is holding

We have to confront our own position. As of 2026-05-21, our internal thesis on Micron is SELL at a $762 reference price, with a conviction score of 2.75 out of 10. The thesis rests on four pillars:

1. NVL72 lockout — Micron holds zero HBM4 allocation in NVIDIA's flagship Vera Rubin VR200 / NVL72 rack architecture, per Castellano and SemiAnalysis.
2. AMD MI455X HBM4 awarded to Samsung — confirmed by the March 18, 2026 AMD-Samsung MoU, displacing the previously assumed Micron primary-supply position for AMD's most HBM-intensive flagship.
3. CXMT supply wave — China's domestic memory entrant is expanding to 290K wafers per month with an additional 120-140K coming in 2026, reaching commercially meaningful yield in 2027.
4. ASP fragility — Castellano's "pricing not demand" framing: the supercycle is price-driven, not unit-volume-driven, and DRAM ASPs have historically fallen 30-50% within six months of cycle peaks.

The bull case in our internal scenario tree is $700. The stock cleared it. The Melius target of $1,100 is roughly 57% above our most optimistic outcome. Either the market has reached escape velocity from the underlying fundamentals, or our thesis has missed a structural change.

This article is the audit.

1.4 What this article does — and does not — do

This is not a buy-sell-hold note. We have not changed our conviction; we are not asking the reader to change theirs. The objective is narrower and, we think, more useful: to expose the technical foundations on which today's supply-demand reality for HBM rests, then stress-test those foundations against the three forces that could undermine them — accelerator architecture (the rise of custom ASICs), model architecture (sparsity, state-space models, test-time compute), and system topology (NVL72's scale-up paradigm, optical interconnect, CXL pooling).

Where consensus has it right, we will say so. Where consensus may be wrong, we will name the failure mode. Where the question is genuinely undecided, we will name the resolution window.

The article presents a thesis — the SCA reframe and the secular elongation of the memory cycle — and an antithesis — Micron's structural allocation lockout across the largest 2026-2028 HBM sockets. Both are real. They live on different axes of the HBM story. The point of this exercise is not to declare a winner. It is to identify where the synthesis lies — what has to be true in the world for one side to dominate — and to name the specific 2027 events that will close the question.

This is what we mean by the 2027 crux. HBM4E base-die qualification, Vera Rubin Ultra allocation, AMD MI500 supplier selection, the OpenAI Titan HBM4 socket, the identity of Mehrotra's first 5-year SCA partner — these are the resolution variables. Not the next analyst price target.

1.5 How to read this

The article proceeds in three movements:

• Part 1 (Chapters 2-3) — the technical foundation. Why HBM exists, why NVL72 became the canonical rack-scale embodiment of the current paradigm, what the supply-demand math actually rests on.
• Part 2 (Chapters 4-7) — the dialectic. Mehrotra's structural argument (Chapter 4), and three stress tests against it (ASIC, algorithm, topology, Chapters 5-7).
• Part 3 (Chapters 8-10) — the synthesis. The 2027 HBM4E crux and the watch list it implies (Chapter 8), the dialectical readout of what we believe and what we do not (Chapter 9), and methodology (Chapter 10).

We use the first-person plural throughout. "We" refers to Theta — the research and judgment that backs the conclusions you read here. Where individual sources contributed specific evidence, we cite them inline. The dossier files on which this article rests sit in our handoff archive and are available on request.

A second article, to follow this one, will take the inverse approach: assume the consensus narrative is right and ask which names along the HBM manufacturing chain we would own. That work is downstream of this one. The question of what to buy is intelligible only after the question of what is true has been pressed as far as we can press it.

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Chapter 2 — Memory Wall, Redux

2.1 The original memory wall

In 1995, William Wulf and Sally McKee published a paper titled "Hitting the Memory Wall: Implications of the Obvious." Their argument was arithmetic, not exotic. Processor clock speeds were doubling every 18 months; DRAM speeds were improving 7-10% per year; the gap between them was widening by roughly 1.4× per year. The wall, they argued, was inevitable. Within a decade or two, the time spent waiting for memory would dominate the time spent computing, and adding compute would yield no useful work.

The wall arrived, but the industry routed around it. Cache hierarchies grew (L1, L2, L3, then NUMA-aware multi-socket designs). Out-of-order execution and prefetching hid memory latency. DDR generations roughly doubled bandwidth every four to five years (DDR3 to DDR4 to DDR5). And the workloads that mattered most through 2010 — single-threaded application performance, server transaction processing, scientific simulation — were cache-friendly enough that the wall remained a designer's constraint rather than a system's bottleneck.

What changed in the GPU era, and particularly in the LLM era, is that the workloads stopped being cache-friendly. The wall returned, in a sharper form.

2.2 Why parallel compute hits the wall harder

A modern training accelerator — the NVIDIA H100, B200, AMD MI300X family — does not look like a CPU. A CPU has on the order of 16-128 cores, each running a few threads, sharing tens of megabytes of cache. A B200 carries 208 Streaming Multiprocessors, hundreds of thousands of FP8 arithmetic units, and only ~256 MB of L2 cache distributed across the package. The arithmetic-to-memory ratio is fundamentally different. Where a CPU has roughly one byte of cache per arithmetic operation per second, a B200 has approximately one-hundredth of that.

That ratio defines the problem. Each arithmetic unit, every clock, needs data. If the data is not local — not in registers, not in the small shared memory of an SM, not in L2 — it must traverse off-die memory. For a CPU that off-die memory is DDR DRAM at hundreds of gigabytes per second. For a GPU it is HBM at multiple terabytes per second per package. The difference is roughly an order of magnitude, and the entire economic case for HBM rests on this gap.

Whether terabytes per second is enough is then the right question. For dense matrix multiplication of activations and weights inside a standard transformer layer, the honest answer is "barely." For sparse compute — MoE expert routing, attention's all-to-all communication, KV-cache traversal during autoregressive generation — the answer is often "no, but we use the bandwidth anyway because nothing else is available."

2.3 Attention's O(n²), and the KV cache

A transformer model computes attention as a softmax over all pairs of tokens in a sequence. For a sequence of n tokens with head dimension d, this is O(n²·d) compute and O(n²) memory traffic during the attention step itself. Pre-LLM, n was small — 32, 64, 128 tokens for translation models. At 8K context, n² is 64 million. At 128K, 16 billion. At 1M, 1 trillion.

But the structurally important number is not the attention compute. It is the KV cache. Decoder-only language models cache the key and value projections for every token they have already seen, so each new token in the autoregressive sequence requires loading the entire history's KV cache from HBM into on-chip SRAM, computing one row of the attention, and writing one new token's K and V back. For a 70-billion-parameter model at 1-million-token context in FP16, that cache is approximately 135 GB — larger than the model weights themselves.

The KV cache is bandwidth-bound. There is no clever algorithm that avoids reading the entire history's projections for every new token. Compression and quantization (FlashAttention, paged attention, KV quantization down to 4 or even 2 bits) reduce the constant factor — TurboQuant claims up to 6× — but the asymptotic dependence on cache size remains.

As inference shifts toward reasoning models — the OpenAI o-series, DeepSeek R1, Anthropic extended thinking, Gemini Thinking — where chains of thought run for tens of thousands of tokens per query, KV cache becomes the dominant memory traffic. DeepSeek disclosed that R1-0528 doubled average AIME token spend from 12K to 23K per question; Morgan Stanley estimates that inference will reach two-thirds of total AI compute by 2026, with reasoning-mode workloads driving the marginal share. Bandwidth, not capacity, becomes the choke point during reasoning generation. We will return to this distinction in Chapter 6 because it cuts in a counter-intuitive direction.

2.4 HBM as the architectural response

The high-bandwidth memory standard exists because conventional DRAM packaging cannot deliver the bandwidth-per-watt the parallel-compute era requires. HBM achieves its bandwidth advantage through three physical decisions: stacking DRAM dies vertically with through-silicon vias, placing those stacks on a logic base die that handles I/O conversion, and positioning the whole assembly on an interposer immediately adjacent to the compute die rather than at the end of a motherboard memory channel.

The math is illustrative. A standard DDR5 module runs roughly 50-60 GB/s per channel. An HBM3 stack delivers approximately 1 TB/s on its own. A current Blackwell B200 carries eight HBM3E stacks for 192 GB capacity and roughly 8 TB/s aggregate bandwidth. NVIDIA's announced Rubin GPU — the chip at the heart of NVL72 — carries eight HBM4 stacks at 288 GB and approximately 22 TB/s. The next generation, Rubin Ultra, is targeted at up to sixteen stacks per package for as much as 1 TB capacity. The trajectory is roughly 3.5× per-package HBM capacity from B200 to Rubin Ultra over two and a half years.

The point is not to celebrate the engineering. The point is that bandwidth-per-package has become an architectural constant that every shipping and announced AI accelerator is designed around. NVL72 sits at one end of the current curve, Rubin Ultra at NVL576 at the other. The supply-demand for HBM in 2026-2028 is, mechanically, the supply-demand for the dominant accelerator path's packaging choice — multiplied by hyperscaler capex.

This is the simple version of why memory has become the focal point of an industry whose marketing has historically belonged to compute. Compute, on a per-flop basis, has stopped being the bottleneck. Memory is.

2.5 Three suppliers, three positions

There are exactly three suppliers capable of manufacturing HBM at the volume, yield, and qualification grade that NVIDIA, AMD, and the hyperscaler ASIC programs require: SK Hynix, Samsung Electronics, and Micron Technology. Their positions going into the 2027 cycle are not equal.

SK Hynix qualified HBM4 at 12-Hi 36 GB at 11 Gbps for NVIDIA in February 2026 and showcased 16-Hi 48 GB at 11.7 Gbps — industry-fastest — at CES 2026. Per Castellano and SemiAnalysis, SK Hynix sits at approximately 70% of Vera Rubin VR200 HBM4 allocation. It has also begun mass production of SOCAMM2 LPDDR5X modules for the Vera CPU side of the same rack, extending its socket position into the LPDDR adjacency.

Samsung Electronics matched the 11 Gbps qualification and started HBM4 mass production in February 2026, with a 250K-wafer-per-month capacity target by year-end. Its 16-Hi parity timeline is gated by hybrid-bonding yield (currently ~10% prototype per industry sources), but it won AMD's MI455X HBM4 primary supply via the March 18 MoU — the most-HBM-intensive non-NVIDIA accelerator of the next generation.

Micron crossed 11 Gbps on its HBM4 12-Hi in late 2025; mass production ramp targets Q2 2026, with 16-Hi by Q4 2026 per NVIDIA's stated cadence. But Micron's allocation in the flagship Vera Rubin VR200 socket is, per the most-cited industry sources, zero. Its HBM4 revenue concentrates in the mid-tier Rubin CPX socket and in residual programs where co-source is permitted. Micron's HBM4E plan includes migrating the base die to a TSMC partnership beginning 2027 — a strategic decision we will return to in Chapter 8, because it intersects directly with the synthesis we are building toward.

These are the relative positions. They are not buy-sell signals. They are the geometry that determines what the SCA reframe can and cannot mechanically do for any one of the three.

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End of Chapters 1-2 draft. Subsequent chapters in queue: Ch 3 NVL72 — The Current Embodiment; Ch 4 The SCA Reframe — Mehrotra's Move; Chs 5-7 Stress Tests (ASIC / Algorithm / Topology); Ch 8 The Crux at 2027 HBM4E; Ch 9 Dialectical Synthesis; Ch 10 Methodology Note.